Digital circuits frequently use a bus line (or simply, "bus") to couple a logical high ("1") or logical low ("0") signal to various circuits or loads. Some examples include a data bus, an address bus, and the like in a central processing unit ("CPU"), or a refresh signal for use with a volatile digital memory.
In many applications, a precharge transistor is coupled between the bus and a known voltage level, typically the upper power supply voltage Vdd. The bus and precharge transistor are typically fabricated on a common integrated circuit chip. Many pulldown load transistors are also coupled to the bus. During precharge mode, the precharge transistor turns on, pulling the bus up to the Vdd level, or at least to a level representing a logical "1" e.g., .gtoreq.22.3 VDC in a 3 VDC system. After precharge mode, any one of the pulldown load transistors can turn on, to pull the bus down to a "0" level, e.g., .ltoreq.1.3 VDC in a 3 VDC system. In the prior art, bus shunt capacitance is large and therefore large, high current, pulldown load transistors are required if the bus is to be pulled rapidly down to "0".
A bus line may be represented by many sections of series-coupled resistance ("R") and shunt-coupled capacitance ("C"), which sections are distributed along the length of the bus. Often busses are relatively long and heavily loaded, being coupled to many output loads that contribute substantial effective load capacitance that stores charge. A problem, toward which this application is directed, is how to rapidly discharge or pull down a bus line from a precharged "1" level to a "0" level, especially when substantial capacitance must be discharged.
FIG. 1A depicts a prior art bus system as containing a bus, a bus pull-up precharge transistor M1, and several output load pulldown transistors M101, M102, M103, M104. Precharge transistor M1 receives a precharge signal nprc, which is "0" for precharge in the configuration shown. When nprc=0 at time tp, transistor M1 turns on and pulls-up the bus to Vdd, pre-charging it to at least a logical "1" voltage level.
Precharge mode, e.g., the time during which nprc turns-on M1, is a fraction of the total clock cycle time associated with the circuit, for example 25%, which may correspond to a precharge pulse width of about 5 ns to 10 ns. During precharge, the bus sees a low drive impedance, namely the output impedance of voltage source Vdd in series with the source-drain impedance of M1.
Precharge ends when nprc goes high, whereupon the precharged bus essentially floats in a "1" state and sees a relatively large impedance. For ease of understanding, the simplified bus waveform in FIG. 1A shows a decay after precharge mode ends (and before bus pulldown occurs at time t4). In practice, however, the bus can remain at a "1" level due to capacitance shunting the bus and due to keeper-type circuitry, not herein relevant. The "1" level bus condition can exist until such time as a pulldown transistor is turned on by its input signal, and pulls the bus to a "0" state, for example at time t4. Prior art bus pulldown characteristics will be described more fully with respect to FIG. 1C.
Although only four pulldown load transistors (M101-M104) are shown in FIG. 1A, it is understood that tens of thousands of such pulldown load transistors may be present. These transistors function together as a wired OR gate in that any one of them can pull the bus down to a logical "0" state. For example, in FIG. 1A, at time t.sub.4 the bus is pulled low by one of the pulldown load transistors, e.g., M104, whose gate has received a "1" input signal, e.g., IN4.
FIG. 1B represents an equivalent circuit for the prior art configuration of FIG. 1A, and depicts the distributed RC bus loading referred to earlier. For ease of illustration, only one of potentially many pulldown transistors is depicted, namely M104. In FIG. 1B, X1, X2 and X3 refer to various nodes present within the distributed RC equivalent bus circuit, with X3 denoting the extreme bus end most remote from M104. While FIG. 1B approximates the bus as having four distributed RC sections, in reality there are N distributed RC sections, where N approaches infinity.
In the four-section analysis of FIG. 1B, the pulldown time constant seen by pulldown load transistor M104 is 4.multidot.(R/4).multidot.4.multidot.(C/4)=1RC. Using a typical value for R of 2 K.OMEGA., and a typical value for C of 7.2 pF, the RC time constant is about 14.4 ns. When M104 turns on, there will be a signal propagation delay before node X3 capacitance can discharge from a logical "1" down to a logical "0". This signal propagation delay will be the delay resulting from the turn-on or transistor M104, plus the time constant delay across the bus, here 1RC. It will be appreciated that as the bus length increases, effective load capacitance also increases and additional delay or skew accumulates.
In the simplified bus shown in FIG. 1B, at time t4, pulldown load transistor M104 is turned on by input signal IN4, and begins to pull nodes X3, X2, bus and X1 down toward a "0" level. If the bus had no distributed RC, the nodes and bus level could be pulled toward "0" relatively rapidly without the load pulldown transistor having to sink substantial discharge current. Unfortunately, such is not the case and in practice the pulldown load transistors must be large devices that can sink substantial drain-source current.
FIG. 1C is a SPICE analysis of the pulldown response of nodes X1, bus, X2 and X3 for the prior art circuit of FIGS. 1A and 1B. This computer simulation assumes a relatively large sized metal-on-silicon load pulldown transistor having a field effect gate width/length ratio ("W/L") of about 80, and an effective capacitive load of about 7.2 pF. It is understood in FIG. 1C that precharge mode has come and gone, and that the bus and nodes X1, X2 and X3 have been pulled up to "1", e.g., .gtoreq.2.3 VDC. After precharge ends and before any pulldown load transistor turns on, the bus sees a relatively large impedance in that M1 and M104 (as well as any other pulldown load transistor) are floating rather than conducting.
In FIG. 1C, at approximately time=-1 ns, a gate input signal ("IN") to a pulldown load transistor goes high (here, IN4="1"), which turns on the corresponding pulldown load transistor (here, M104). If there were no distributed RC, node X1, bus, node X2 and node X3 could instantly be pulled low. However, as shown by FIG. 1C, due to the effect of the distributed RC, node X1 is first pulled low, then the bus node, then node X2, and finally the most remote node, node X3.
FIG. 1C indicates that it takes T.sub.d .about.8 ns for the voltage at node X3 to be pulled from a "1" state (e.g., .gtoreq.2.3 VDC) to a "0" state (e.g., .ltoreq.1.3 VDC), relative to when IN.about.1.3 VDC. It is understood that as the bus length is increased or as more capacitive loads are coupled to the bus, pulldown time T.sub.d is extended and rapid bus pulldown becomes more difficult to attain. To substantially shorten T.sub.d requires that the pulldown load transistors be capable of sinking substantial drain-source current. This in turn requires the pulldown load transistors to be relatively large devices having a W/L ratio of about 50 or more.
Thus, one disadvantage of the prior art configuration of FIGS. 1A-1B is that the various pulldown load transistors M101, M102, etc., must be large devices capable of sinking substantial current i.sub.pulldown, if rapid bus pulldown is to be achieved. This statement is true because i.sub.pulldown .about.C.sub.equivalent .DELTA.V/.DELTA.T, where .DELTA.V/.DELTA.T represents the pulldown transition rate, and C represents the total equivalent load capacitance shunting the bus.
However, requiring the pulldown load transistors to sink large pull-down current is undesirable because current surges and ground bounce transients can occur, to the detriment of other signals in the system. Further, having to fabricate many large sized pulldown load transistors leaves less integrated circuit chip area for fabricating other portions of the circuitry. Also, as the pulldown load transistors increase in size, they contribute still more load capacitance to the bus, compounding the problem of rapid bus pulldown.
In summary, what is needed is a method and apparatus whereby the effective distributed resistance and capacitance associated with a bus can be reduced. The resultant bus could then be pulled-down using less pulldown current, ipulldown, thereby permitting the use of smaller W/L pulldown load devices that would reduce current surge and ground bounce. Further, the use of smaller pulldown load devices saves integrated circuit chip area, and presents less capacitive loading to the bus.
The present invention provides such a method and apparatus.